This invention relates generally to computer operation monitoring, and more particularly to a monitor providing a continuously active assessment of the performance of a parallel communications bus.
Monitoring of computer operations for assessment of reliability has been widely employed in the data communication arts. Numerous monitoring schemes are employed in computers whereby comparators are utilized for comparing data with a reference or nominal value and generating an error signal in the event of mismatch. Computer program subroutines are employed whereby, for example, the data stored in a particular memory address or in a complete memory bank might be periodically checked with comparison values to assure that the data stored matches that which was intended to be stored. In Auspurg U.S. Pat. No. 3,869,603, a test control includes a register for storing manual information applied in successive cycles to a storage unit under test, along with a comparator for comparing the nominal values read into a storage unit with the data read out therefrom, and means for generating an error signal in the event of a mismatch. Carita U.S. Pat. No. 3,712,537 teaches an apparatus for detecting faults in the selection circuits of addressable memories, wherein the memory line selection switches are closed according to a predetermined sequence and the pattern of current flow through the switches is indicative of the presence of faults. Dynamic monitoring systems are typified by Giorcelli U.S. Pat. No. 4,030,074, Ling U.S. Pat. No. 3,771,131, and Sargent U.S. Pat. No. 3,309,678, wherein a unit to be tested does not have to be in a "rest" state.
Generally, in the computer monitoring art, monitoring is accomplished by a program subroutine or, alternatively, redundant computations are employed with a subsequent comparison therebetween to annunicate disagreement.
The present invention is related to the provision of a monitoring approach for data processing systems of the type employing a plurality of devices each interfacing with common address data and control buses. The common bus interconnects the various processors memories and peripheral devices with data transfer between any pair of devices being possible without processor intervention. These types of systems are currently employed in the art and might be termed adaptive processing systems.
In an adaptive processing system, communications between devices on the common bus is in the form of a master-slave relationship, and at any point in time only one device can have control of the bus. To complete data transfers, the master (controlling) device waits for a response from the slave (addressed) device. Potential masters connected to the transfer bus compete for control through a positional priority scheme. A known system of this type is described in a publication entitled "Collins Adaptive Processing System (CAPS) Transfer Bus" a publication of Collins Avionics Group/Rockwell International Corporation, publication number 523-0768040-001117, dated July 15, 1977. In this type of system, two classes of devices connect to a common transfer bus which includes address and data parallel lines. Master devices connect to the buses and control data transfers, while slave devices supply or accept data in response to a master's request. Data transfers in either direction always occur between one master and one or more slaves. There may be several slaves and potential masters on the same bus, and the masters are dynamically activated one at a time as their need for a data transfer arises. A central processing unit is a typical master device while a memory module would be classified as a slave device. In this type of system, if the CPU is to have even rudimentary intelligence, it is manditory for the common transfer bus to function correctly. Typically, the common bus interfaces with each of the slaves and masters via buffering interface devices, and should any one of these interface devices fail, to a low state for example, any ensuing computation is invalid. In present usages, as in a multichannel, fault tolerant, computational system, it is imperative that any failure of one computation channel be recognized and immediate remedial action taken. In this way, the accumulation of faults in the multiple channels is prevented and orderly system degregation and recovery are insured. For example, in an autopilot system, the failure of an interface device communicating with a common transfer bus completely destroys the computation ability of the system, and the detection of such failure might be utilized to initiate a system shutdown and disconnect for purposes of safety. The need arises, then, for a monitoring system for such a common parallel communication bus which will annunciate bus fault conditions on a dynamic basis without interference with the normal computation activity of the system.
Uniquely, in the above referenced and described adaptive processing systems, there exists in the common control bus between master and slave devices a discrete control line exhibiting first and second logic levels respectively indicative of whether the bus is "busy" or "at rest". Here the term "busy" infers that the parallel lines in the data and address buses are being utilized for a data transfer and/or addressing purposes, while the term "at rest" infers that the data and address bus lines are not being so employed. During "at rest" intervals, a predefined logic level, as defined by the system interfaces to the bus, exists on the lines. For example, during conditions of the bus being "at rest", all lines in the bus, as established by the bus interface circuitry, might be at a zero logic level or alternatively, at some system defined permutation of binary levels.